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Title A 90.9% Efficient 4-phase Interleaved Charge Pump Topology with FBB and Internal Clock Boosting Technique for Energy Harvesting Applications
Posted by Ritt Vincent Librado
Authors Librado, Ritt Vincent ; Hora, Jefferson
Publication date 2022/12/20
Conference IEEE REGION 10 CONFERENCE 2022 (TENCON 2022)
Publisher IEEE
Abstract A monolithic 4-phase Interleaved Charge Pump (ICP) Topology is proposed for low-input Energy Harvesting applications. With the varying ambient energy density across different terrain and environment, harvesting remains critical, especially when harvested power falls below nominal operating levels of Power Management Units (PMUs); a low-Vin ICP architecture is proposed to boost available voltage levels to supply succeeding PMU blocks. The proposed design is applied in a 4-phase clocking scheme to eliminate all reversion losses using an integrated clock booster, eliminating the use of level shifters for PMOS gate control, eliminating voltage overstress and breakdown issues while optimizing the design for scalability. Furthermore, a Forward Body Bias (FBB) technique is applied to the proposed architecture to accommodate low-input power conditions. The proposed ICP is implemented using TSMC 65nm process technology and can accommodate inputs as low as 250mV. Measured results showed an improved PCE of 90.9%, 80.95 %, and 77.47% for single-stage, dual-stage, and triple-stage ICP implementation at low-input power of approximately 140uW.
Index terms / Keywords CMOS , Charge Pump , Interleaved Charge Pump(ICP) , Cross-Coupled Voltage Doubler (CCVD) , Energy Harvesting
DOI 10.1109/TENCON55691.2022.9977687