Conference
| Title | An Area-Efficient and Low-Power Comparator for Type-III Compensated Voltage-Mode Control DC-DC Buck Converter in 65nm CMOS Technology Process Posted by Aileen Gumera |
| Authors | Ecclesiastes G. Montaos ; Aileen B. Caberos ; Leocarl M. Viñalon |
| Publication date | 2019/11/21 |
| Conference | 2019 19th International Symposium on Communications and Information Technologies (ISCIT) |
| Pages | 113-117 |
| Publisher | IEEE |
| Abstract | This paper presents an area-efficient and low-power comparator for application in the PWM stage of a type-III-compensated voltage-mode control DC-DC buck converter. The comparator is made up of only 4 transistors and is implemented in TSMC 65nm CMOS technology. The four-transistor comparator exhibits a power consumption of only 0.67 μW and a layout area of 13.88 μm 2 - values much smaller as compared to two existing conventional comparator architectures. Also, the application of the four-transistor comparator significantly lessens the power consumption and design complexity of the control feedback of the DC-DC buck converter without affecting the overall performance of the converter. |
| Index terms / Keywords | Comparator, DC-DC Buck Converter, Pulse Width Modulation, Voltage-Mode Feedback Control |
| DOI | DOI: 10.1109/ISCIT.2019.8905205 |
| URL | https://ieeexplore.ieee.org/document/8905205 |