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Title Area-efficient CMOS implementation of NCL gates for XOR-AND/OR dominated circuits
Posted by Aileen Gumera
Authors Aileen Caberos, Shu-Chuan Huang, and Fu-Chiung Cheng
Publication date 2018/02/05
Conference 2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)
Pages 37-40
Publisher IEEE
Abstract This paper presents an area-efficient CMOS implementation of Null Conventional Logic (NCL) gates for XOR-AND/OR dominated asynchronous circuits. These optimization of logic gates are based on Binary Decision Diagram (BDD) that produces 25% and 14.29% fewer transistor counts for the proposed logic topology of XOR and AND/OR respectively. Thus, giving a reduced area of more than 14% compared with the conventional NCL logic circuits. The simulation results show the delay and energy consumption can give a reasonable result as compared to conventional approach.
Index terms / Keywords Null Convention Logic (NCL), C-element, Dual-rail signal, CMOS gate design
DOI DOI: 10.1109/PRIMEASIA.2017.8280358