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Title A Modified Yadav CMOS Buffer for SRAM Design
Posted by Aileen Gumera
Authors Leocarl M. Viñalon ; Aileen B. Caberos ; Olga Joy L. Gerasta
Publication date 2019/11/21
Conference 2019 19th International Symposium on Communications and Information Technologies (ISCIT)
Pages 122-126
Publisher IEEE
Abstract Significant amount of the total power consumption in on-chip SRAM comes from leakage power. As technology sizes down, maintaining high-speed performance at the same time making effort to curtail leakage power has become more and more challenging. The goal of this work is to curtail leakage power in SRAM peripherals, particularly in word line drivers. The proposed buffer architecture is a merger of 4-stage CMOS buffer without dynamic short-circuit power dissipation and reverse body biasing technique. For a load capacitance of 150 fF and input clock frequency of 100 kHz, the technique results to a static power reduction of 5 pW. Comparison shows that the proposed buffer offers a 10.26% reduction in total power consumed.
Index terms / Keywords SRAM, CMOS buffer, leakage power, body bias, Yadav
DOI DOI: 10.1109/ISCIT.2019.8905221