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Conference

Title A 500MHZ Delay-Locked Loop with Start-Controlled Phase-Frequency Detector
Posted by Allenn Lowaton
Authors Renee Anne Albarracin; Rafael S. Gamo; Nieva M. Mapula; Allenn C. Lowaton
Publication date 2016
Conference 9th Regional Conference on Electrical and Electronics Engineering
Volume 1
Issue 1
Pages 221-226
Publisher BACH KHOA PUBLISHING HOUSE
Abstract A delay-locked loop with start-controlled phase frequency detector was designed and simulated in 180nm CMOS technology. The DLL that operates in 500MHz was implemented with a start-controlled Phase frequency detector having a very small dead-zone of 5ps. This research can be used in applications such as signal processing, ADCs and microprocessors. The charge pump follows the concept of current steering technique that is more suitable for high-speed operations and decreases the severity of current mismatch problems. The Voltage Controlled Delay Line utilizes high resolution current-starved delay elements, thus seven delay elements connected in series was used and a large output buffer was incorporated at the output of the VCDL. The current-starved delay element was designed for narrow band frequency. At 500MHz, the proposed DLL has a frequency range 490-510MHz, locks at 27 clock cycles, a jitter of 85.2ps and a duty cycle error of ±4%. The dimension of over-all chip layout is 133.32μmx168.57μm.
Index terms / Keywords Dead-zone, phase-frequency detector, delay-locked loop, duty cycle, jitter, lock range, lock time
URL https://www.researchgate.net/publication/313649941_A_500MHZ_Delay-Locked_Loop_with_Start-Controlled_Phase-Frequency_Detector