A 90.9% Efficient 4-phase Interleaved Charge Pump Topology with FBB and Internal Clock Boosting Technique for Energy Harvesting Applications

Title	A 90.9% Efficient 4-phase Interleaved Charge Pump Topology with FBB and Internal Clock Boosting Technique for Energy Harvesting Applications Posted by Ritt Vincent Librado
Authors	Librado, Ritt Vincent ; Hora, Jefferson ; Kevin O. Maglinte
Publication date	2024/01/03
Conference	2023 22nd International Symposium on Communications and Information Technologies (ISCIT)
Publisher	IEEE
Abstract	A multistage implementation of an Interleaved Charge Pump (ICP) Topology is used in this paper in a 4-phase clocking scheme to optimize the design for scalability, eliminate all reversion losses, and eliminate level shifters for PMOS charge transfer switch (CTS) control to reduce voltage overstress and breakdown concerns. In addition, to address low-input power conditions, an ICP topology for startup and bulk modulation techniques are applied to the ICP design. Furthermore, The designs are capable of supporting inputs as low as 250mV, and extended load ranges, implemented utilizing TSMC’s 65nm process technology. At a low input power roughly 140uW, measured data indicated a peak PCE of 90.9%.
DOI	10.1109/ISCIT57293.2023.10376133
URL	https://ieeexplore.ieee.org/document/10376133